Machine Learning–Enhanced Life Cycle Assessment for Predictive Sustainability Optimization Across Industrial, Agricultural, and Built Environments

Digital Very LargeScale Integration (VLSI) design has become increasingly complex due to the rapid growth of semiconductor technology, system-on-chip (SoC) architectures, hardware security requirements, and low-power computing applications. Simulation tools play a significant role in validating hardware functionality, timing behavior, power optimization, and security verification before fabrication. Among the widely used simulators in VLSI design environments are Cadence Verilog-XL, Cadence NCSIM, and Mentor Graphics ModelSim. These simulators provide different levels of performance, simulation speed, debugging capability, memory efficiency, and support for modern verification methodologies. This paper presents a comparative performance analysis of Cadence Verilog-XL, NCSIM, and ModelSim for digital VLSI simulation. The analysis is based on simulation execution time, memory utilization, waveform generation, debugging capability, hardware security validation support, scalability, and compatibility with contemporary VLSI workflows. The paper also discusses the role of Electronic Design Automation (EDA) tools in secure hardware composition and verification. Experimental observations indicate that NCSIM provides superior runtime efficiency and scalability for large-scale digital circuits, while ModelSim offers strong debugging support and educational usability. Verilog-XL remains useful for legacy verification environments despite limitations in performance and modern feature support. The study highlights the importance of selecting appropriate simulation tools according to design complexity, verification requirements, and hardware security constraints in contemporary VLSI systems.

VLSI Simulation, Verilog-XL, NCSIM, ModelSim,

A. Ehret, K. Gettings, B. R. Jordan and M. A. Kinsy, “A Survey on Hardware Security Techniques Targeting Low-Power SoC Designs,” 2019 IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, USA, 2019, pp. 1–8.

A. Shamsoshoara., A survey on physical unclonable function (PUF)-based security solutions for Internet of Things, Computer Networks, Volume 183, 24 December 2020.

Gu, C., Liu, W., Hanley, N., Hesselbarth, R., & O'Neill, M. ( 2018 ). A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations. IEEE Transactions on Computers, 68 ( 2 ), 287.

Heather Adkins Building Secure and Reliable Systems, O'Reilly Media, (online).

H. Liu, Methods for Estimating the Convergence of Inter-Chip Min-Entropy of SRAM PUFs, IEEE Trans. On Circuits and Systems-I, Vol. 65, No. 2, Feb 2018.

https://arxiv.org/pdf/1209.3744.pdf (min entropy).

https://openai.com/blog/chatgpt.

https://research.checkpoint.com/2023/opwnai-cybercriminals-starting-to-use-chatgpt/.

https://static.googleusercontent.com/media/sre.google/en//static/pdf/building_secure_and_reliable_systems.pdf.

https://www.green-ic.org/physically-unclonable-function-database-pufdb/.

J. Knechtel, “Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA,” 2020 Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, 2020, pp. 508–513.

K. Yang, D. Blaauw and D. Sylvester, “Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey,” in IEEE Micro, vol. 37, no. 6, pp. 72–89, November/December 2017.

M. Gallerger, Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn, Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating SystemsApril 2019 Pages 469–484.

Ryan Kastner, Automating hardware security property generation: invited, DAC '22 : Proceedings of the 59th ACM/IEEE Design Automation Conference July 2022 Pages 1384–1387.

S. L. Lu, Capacitor-based temperature-sensing device, US Patent # 11009404.

TM Mak, Privte communication.

W. Hu, C.-H. Chang, A. Sengupta, S. Bhunia, R. Kastner, and H. Li. 2021. An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. IEEE Trans. on CAD of Integrated Circuits and Systems 40, 6 ( 2021 ).