A Comprehensive Study on Fault-Tolerant RISC-V Architectures and Safety-Aware Cyber-Physical Systems for Reliable Autonomous and Space Computing
Abstract
This article synthesizes contemporary theory and practice in fault-tolerant microarchitectures with a focus on RISC-V processor cores, dual-core lockstep designs, software-implemented redundancy, and latency-aware provisioning in prediction-serving pipelines. Drawing exclusively on the provided literature, it constructs an integrative perspective that links radiation- and transient-fault mitigation strategies from aerospace and satellite applications to safety-critical domains such as automotive zonal controllers and edge prediction services. The structured abstract presents: (a) background emphasizing the confluence of reliability, performance, and cost pressures; (b) methods describing comparative, design-oriented, and analytical approaches distilled from the references; (c) key thematic results synthesizing hardware-and-software co-design patterns, statistical injection frameworks, thread protection techniques, and system-level provisioning trade-offs; and (d) conclusions outlining research directions, practical recommendations, and limitations. This contribution does not present new empirical measurements but offers a deep theoretical elaboration that clarifies design choices, exposes nuanced trade-offs, and proposes a unified framework for future experimental validation and standardization.
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References
- Crankshaw, D., Sela, G. E., Mo, X., Zumar, C., Stoica, I., Gonzalez, J., & Tumanov, A. (2020, October). InferLine: latency-aware provisioning and scaling for prediction serving pipelines. In Proceedings of the 11th ACM Symposium on Cloud Computing (pp. 477-491).
- Dantas, Y. G., & Nigam, V. (2023). Automating safety and security co-design through semantically rich architecture patterns. ACM Transactions on Cyber-Physical Systems, 7(1), 1-28.
- Foudeh, H. A., Luk, P. C. K., & Whidborne, J. F. (2021). An advanced unmanned aerial vehicle (UAV) approach via learning-based control for overhead power line monitoring: A comprehensive review. IEEE Access, 9, 130410-130433.
- Li, J., et al. (2022). Duckcore: A fault-tolerant processor core architecture based on the RISC-V ISA. Electronics, 11(1).
- Blasi, L., et al. (2019). A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled watchdog timer. In APPLEPIES, 2019, pp. 505–511.
- Wilson, A. E., et al. (2019). Neutron radiation testing of fault tolerant RISC-V soft processor on Xilinx SRAM-based FPGAs. In IEEE SCC, 2019, pp. 25–32.
- Santos, D. A., et al. (2020). A low-cost fault-tolerant RISC-V processor for space systems. In DTIS, 2020, pp. 1–5.
- Leveugle, R., et al. (2009). Statistical fault injection: Quantified error and confidence. In IEEE/ACM DATE, 2009, pp. 502–506.
- Fayyaz, M., & Vladimirova, T. (2014). Fault-tolerant distributed approach to satellite on-board computer design. In 2014 IEEE Aerospace Conference. ISSN 1095-323X.
- Ginosar, R. (2012). Survey of processors for space. In DASIA, 2012, pp. 1–5.
- Goloubeva, O., et al. (2006). Software-implemented hardware fault tolerance. Springer Science & Business Media, 2006.
- Abdul Salam Abdul Karim. (2023). Fault-Tolerant Dual-Core Lockstep Architecture for Automotive Zonal Controllers Using NXP S32G Processors. International Journal of Intelligent Systems and Applications in Engineering, 11(11s), 877–885. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/7749
- Gomaa, M. A., et al. (2003). Transient-fault recovery for chip multiprocessors. IEEE Micro, 23(6), 76–83.
- Gomez-Cornejo, J., et al. (2013). Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. In IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, pp. 2261–2266.
- Hagen, W. von. (2006). The Definitive Guide to GCC. 2nd ed. Apress.