VIJAYAPRABHUVEL RAJAVEL. Integrating Power-Saving Techniques into Design for Testability of Semiconductors for Power-Efficient Testing. The American Journal of Engineering and Technology, [S. l.], v. 7, n. 03, p. 243–251, 2025. DOI: 10.37547/tajet/Volume07Issue03-22. Disponível em: https://www.theamericanjournals.com/index.php/tajet/article/view/5997. Acesso em: 3 aug. 2025.